
module RegisterMemory(
  input  wire        clk,
  input  wire        rst_n,
  input  wire [ 3:0] addr,
  input  wire        wr,
  input  wire [21:0] idata,
  output reg  [21:0] odata
);

reg [21:0] rarray_0;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_0 <= #1 22'b0;
    else if((addr==4'h0) && wr)
	rarray_0 <= #1 idata;
end

reg [21:0] rarray_1;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_1 <= #1 22'b0;
    else if((addr==4'h1) && wr)
	rarray_1 <= #1 idata;
end

reg [21:0] rarray_2;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_2 <= #1 22'b0;
    else if((addr==4'h2) && wr)
	rarray_2 <= #1 idata;
end

reg [21:0] rarray_3;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_3 <= #1 22'b0;
    else if((addr==4'h3) && wr)
	rarray_3 <= #1 idata;
end

reg [21:0] rarray_4;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_4 <= #1 22'b0;
    else if((addr==4'h4) && wr)
	rarray_4 <= #1 idata;
end

reg [21:0] rarray_5;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_5 <= #1 22'b0;
    else if((addr==4'h5) && wr)
	rarray_5 <= #1 idata;
end

reg [21:0] rarray_6;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_6 <= #1 22'b0;
    else if((addr==4'h6) && wr)
	rarray_6 <= #1 idata;
end

reg [21:0] rarray_7;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_7 <= #1 22'b0;
    else if((addr==4'h7) && wr)
	rarray_7 <= #1 idata;
end

reg [21:0] rarray_8;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rarray_8 <= #1 22'b0;
    else if((addr==4'h8) && wr)
	rarray_8 <= #1 idata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	odata <= #1 8'b0;
    else 
	case(addr)
        4'h0   : odata <= #1 rarray_0;
        4'h1   : odata <= #1 rarray_1;
        4'h2   : odata <= #1 rarray_2;
        4'h3   : odata <= #1 rarray_3;
        4'h4   : odata <= #1 rarray_4;
        4'h5   : odata <= #1 rarray_5;
        4'h6   : odata <= #1 rarray_6;
        4'h7   : odata <= #1 rarray_7;
        4'h8   : odata <= #1 rarray_8;
	default: odata <= #1 8'b0;	
        endcase		
end

endmodule

